The present invention relates generally to low-power operational amplifiers which have low quiescent current but nevertheless are capable of delivering large output current, and more particularly to amplifier output stages which have low quiescent current but nevertheless are capable of delivering large output current.
FIG. 1 shows a conventional two-buffer input stage voltage feedback operational amplifier 1A. Two-buffer input stage 1A includes a buffer 2 having an input coupled to Vin− and an output 12A coupled by a transconductance element Rgm to the output 12B of another buffer amplifier 3. The input of buffer 3 is coupled to Vin+. Buffer 2 is powered by supply voltages VCC and VEE. Buffer 3 is configured such that a current flowing out of or into its output terminal 12B will be replicated in conductors 5 and 8 and presented to the control inputs of complementary current mirrors 4 and 7. Current mirror 4 is referenced to VCC and current mirror 7 is referenced to VEE. The outputs of current mirrors 4 and 7 are connected by conductor 6 to the input of a unity gain buffer 9. Buffer 9 is powered by VCC and VEE, and produces an output voltage Vout.
By virtue of buffer amplifiers 2 and 3, a differential input voltage present at inputs Vin+ and Vin− is replicated upon the terminals of resistor transconductance element Rgm. Thus, the transconductance of input stage 1A of FIG. 1 is approximately described by the expression Rgm=I1/Vin, where Vin=Vin+−Vin−. Since the small signal bandwidth is equal to gm/Cc and since I1 is replicated by the current mirror and delivered to the compensation capacitor Cc, the large signal bandwidth will be approximately equal to the small signal bandwidth. The output stage of FIG. 1 has the limited output current drive capability of a typical low power bipolar transistor based operational amplifier.
FIG. 2 shows a conventional circuit 30 including a diamond buffer and its associated bias circuitry which together can be used to implement each of buffers 2, 3 and 9 of FIG. 1. The diamond buffer circuitry 30 of FIG. 2 includes diode-connected PNP transistor Q1 having its emitter coupled by resistor R1 to VCC, and its base and collector connected to one terminal of a current source 24 producing a current I and to the base of a PNP transistor Q54. The emitter of transistor Q54 is coupled by resistor R39 to VCC and its collector is connected to the base of NPN output transistor Q74 and to the emitter of PNP input transistor Q57. The base of transistor Q57 is connected to an input signal Vin and its collector is connected to VEE. Another terminal of current source 24 is connected to the collector and base of NPN transistor Q2 and to the base of PNP transistor Q55. The emitter of transistor Q2 is coupled by resistor R2 to VEE, and the emitter of transistor Q55 is coupled by resistor R40 to VEE. The collector of transistor Q55 is connected to the base of PNP output transistor Q75 and to the emitter of NPN input transistor Q58, the base of which is coupled to Vin. The emitters of output transistors Q74 and Q75 are connected to an output conductor 25 through which an output current Io flows. If the various NPN and PNP transistors are assumed to have a maximum DC current gain of β, then the equation for the maximum output current of diamond buffer 30 isIo(max)=β×I. 
FIG. 3 shows a known output stage 31 which includes the diamond buffer circuitry 30 of FIG. 2 and also includes a “β2” (“Beta squared”) circuit 34 which substantially increases the maximum output current that can be supplied by output stage 31. β2 circuit 34 includes a current mirror including diode-connected NPN transistor Q71 having its emitter coupled by resistor R50 to VEE. Instead of being connected to VEE, the collector of diamond buffer output transistor Q75 is instead connected to the base and collector of NPN current mirror input transistor Q71 and to the base of NPN current mirror output transistor Q73, the emitter of which is coupled by resistor R52 to VEE. Similarly, instead of being connected to VCC, the collector of diamond buffer output transistor Q74 is instead connected to the base and collector of PNP current mirror input transistor Q70 and to the base of PNP current mirror output transistor Q72, the emitter of which is coupled by resistor R51 to VCC. The collector of current mirror output transistor Q73 is connected to the base of PNP output transistor Q79 and to the collector of PNP transistor Q76 and the emitter of NPN transistor Q77. Similarly, the collector of current mirror output transistor Q72 is connected to the base of NPN output transistor Q78 and to the emitter of transistor Q76 and the collector of transistor Q77. The bases of transistors Q76 and Q77 are connected together to provide a 2 VBE voltage drop. β2 output circuitry 34 is a class AB output circuit that allows the output drivers to be biased using transistors which require only half of the chip area that would be required if NPN and PNP transistors Q77 and Q76 were to be series-connected. A resistor R56 is connected between the output terminal 36 of β2 output circuitry 34 and the output terminal 25 of circuit 30. Those skilled in the art will recognize that output stage 31 of FIG. 3, including diamond buffer stage Q57,58,74,75 coupled through resistor R56 to β2 output circuitry 34 is a rudimentary unity gain configured current feedback amplifier.
The output stage 31 shown in FIG. 3, assuming the complementary current mirrors have a current gain of 1, is capable of generating an output current as high as I×β2, where I is the collector current flowing in transistors Q54 or Q55. Under quiescent conditions, the current In flowing in the collectors of transistors Q72 and Q73 will be some multiple of I, depending on the ratio set up between the input and output transistors of the diamond buffer and the input and output transistors of the complementary current mirrors. In this example, the diamond buffer has a ratio of 2 from input to output and the current mirror ratios have a ratio of 1 from input to output. Consequently, the current In will be equal to 2I. As the load on output conductor 36 increases, the current In will increase as required by the base of output transistor Q78 or Q79. This occurs via current feedback through resistor R56. Since the current In is also flowing in either the collector of transistor Q74 or Q75, it follows that In can increase until it is β times the maximum current available at the base of transistor Q74 or Q75; that is, the current In can increase until it is equal to β×I. The equation for the output current maximum Io is developed as follows:Io(max)=β×In(max),In(max)=β×I, soIo(max)=β(β×I)=β2×I. 
The circuit 31 of FIG. 3, which is ordinarily used as output stage 9 in the circuit configuration of FIG. 1, has a current feedback based topology, provides β2 current gain capability, and also has good stability when biased dynamically. Dynamic bias also provides good slew rate performance. (Dynamic bias can be implemented by providing additional outputs for the current mirrors, respectively. For example, in FIG. 1, this would be shown as a second output of each of current mirrors 4 and 7. The additional outputs would be used to bias output stage 9. During a slew condition the additional outputs provide additional boost to output stage 9. Even though output stage 31 of FIG. 3 is capable of β2 current gain, it may be the case that an operational amplifier such as that depicted in FIG. 1 is required to specify a minimum output current capability which is greater than that able to be provided by the output stage of FIG. 3 with a given quiescent current.)
There is an unmet need for an operational amplifier capable of producing substantially increased output current without requiring substantially increased quiescent current.
There also is an unmet need for an output stage capable of producing substantially increased output current without requiring substantially increased quiescent current.